Abstract
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
Highlights
Over the last three decades, designs using multiple-valued logic have been receiving considerable attention [1]
VLSI architecture is developed for his new algorithm to perform finite field arithmetic operations [8]
Down literal circuits are realized from basic CMOS inverter by changing the threshold voltages of pmos and nmos transistors as shown in figure 1
Summary
Over the last three decades, designs using multiple-valued logic have been receiving considerable attention [1]. The history of Multiple-valued logic (MVL) as a separate subject began in the early 1920 by a polish philosopher Lukasiewicz. His intention was to introduce a third additional value to binary. In modern SOC design, the interconnection is becoming a major problem because of the bus width. This problem can be solved by using Multiple-valued logic interconnection. Quaternary signals are converted to binary signals before performing arithmetic operations. Results of arithmetic operations are binary signals These binary signals are to be converted to quaternary signals. Quaternary to binary and binary to quaternary converter are designed, and Modulo-4 arithmetic operations are performed in such a way to get minimum number of gates and minimum depth of net
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