Arithmetic Circuit Correction by Adding Optimized Correctors Based on Groebner Basis Computation

Abstract

Although Symbolic Computer Algebra (SCA) is a promising approach to verify large arithmetic circuits, automatic correction of such circuits based on SCA remains a significant challenge due to the monomial explosion. SCA-based verification methods translate the circuit and the specification into a set of polynomials. The verification problem is considered as an ideal membership test for the given specification polynomial where the ideal is generated by the polynomials of the circuit. A polynomial, called the remainder, is returned by the verification algorithm whose value shows the correctness of the circuit. Our main idea to automatically correct the buggy circuit is to construct a sub-circuit called the corrector, implementing the complement of the remainder, which is added to the buggy circuit. Our method is applied to various multiplier circuits, with different sizes (8 to 256 bits) and the number of bugs (1 to 5 bugs). The proposed method is compared with a method, which eliminates one term of the remainder in each step by inserting elements to the circuit to achieve a zero remainder. The results show that generating the corrector sub-circuit is done, on average, 20.03× faster than before applying our method.