Area-speed efficient modular architecture for GF(2<sup>m</sup>) multipliers dedicated for cryptographic applications

Abstract

Arithmetic operations over GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) have wide applications in many domains, especially in cryptography. Cryptographic applications of GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) arithmetic units are the most demanding applications. The binary finite field extension multipliers are components of elliptic curve cryptography (ECC) systems and perform crucial operations in the system. In fact all operations in the system are sequences of operations in the finite field. Thus, the efficiency, in terms of speed and area of the finite-field units, significantly impacts efficiency of ECC systems. In this paper we propose a modified approach to construction of area-speed efficient modular GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) multiplier operating on fields of large sizes defined in cryptographic standards (thus on large numbers c. 160-600 bits), which leads to increase of the overall area-speed efficiency of the architecture. To increase the efficiency of the multiplier we have combined bit-parallel and bit-serial manner of processing input operands. The proposed architecture is modular; it does not require redesign of the multiplier if we decide to change the field size used. We present two architectures, dedicated to FPGA circuit, of modular block which constitutes the proposed GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) multiplier. The article details variations of the multiplier architecture, which impact its speed or area and shows how its parameters scale for different field sizes.