Area-oriented iterative method for Design Space Exploration with High-Level Synthesis

Abstract

To assure good quality of synthesis results (QoR) in the current High-Level Synthesis (HLS) practice is still a big challenge. To address the issue of very large design space possibilities in digital systems design, this paper presents an iterative method for Design Space Exploration (DSE). We target FPGA (field-programmable gate array) devices and use an off-the-shelf standard HLS tool in our experiments. We present our methodology, which includes: code optimization checkpoints detection, automatic optimization directives insertion and results parsing/analysis aiming at a highest QoR, in terms of area. Experimental results on HLS compilation of a VLIW (Very Large Instruction Word) processor obtains up to 68% on flip-flops (FFs) reduction and 32% of lookup-tables (LUTs) reduction, compared to a baseline HLS flow. Using a FIR filter HLS as a test-case, our DSE method with the same Vivado™ tool results in more than 3X lower FF utilization, with practically the same LUTs consumption and performance, comparing with the non-guided HLS flow. Our results, in terms of QoR, represent an increase of 50% and 43%, respectively, for VLIW and FIR filter benchmarks.