Area-efficient STT/CMOS non-volatile flip-flop

Abstract

An area-efficient non-volatile flip flop (NVFF) is proposed. The proposed NVFF is comprised of two storages: a conventional flip flop as a static storage during the power-on and a spin-torque transfer magnetic tunnel junction (STT-MTJ) as a temporary storage during the power-off. The area overhead of the MTJ block is minimized by reusing a part of the existing flip flop. The energy overhead for the temporary storage is reduced by a current reuse technique. We evaluated the proposed NVFF circuit using a compact MTJ model targeting an implementation in a 10nm technology node. Results indicate that area overhead is 6.9% normalized to the conventional flip flop and that the energy overhead is 0.2pJ. Compared to the best previously known NVFFs, the proposed circuit succeeded in reducing the area by 4.1× and the energy by 1.5×.