Area-efficient parallel white Gaussian noise generator

Abstract

We propose an area-efficient field-programmable gate array (FPGA) implementation of a Gaussian noise generator (GNG) that is based on the Box-Muller algorithm. The compact GNG can be realized on the same FPGA chip as the circuit under test to allow digital communication systems to be accurately characterized. An efficient implementation of a pseudo-random number generator is utilized that reduces FPGA resource utilization. Also, on-chip block memory is used efficiently to improve the noise quality. The implemented design on a Xilinx XC2V4000-6 FPGA utilizes only 3% of the configurable resources and operates at up to 165 MHz. The parallel, configurable and scalable datapath of the GNG offers trade-offs between sampling rate and area