Area-Efficient Delay-based PUF Based on Logic Gates

Abstract

As a promising circuit primitive, Physical Unclonable Function (PUF) draws extensive attention and research. PUF can extract features of integrated circuits (ICs) from random process variations and be applied for identification, device authentication and secret key generation, etc. To improve the security of PUF, the outputs of independent PUFs are XOR-mixed together, which requires more circuits. In this paper, we propose an area-efficient delay-based PUF based on logic gates, which exploits delay differences of logic gates. To improve the security of the PUF, an output network is designed to combine the outputs from multiple delay lines. It has been demonstrated that the PUF satisfies the Strict Avalanche Criterion (SAC) and can pass NIST randomness test. SPICE-based evaluation using TSMC 65nm technology validates the high uniqueness of the PUF. Synthesized results with the Synopsys Design Compiler of PUFs using TSMC 65nm technology validate their low area overhead.