Area-delay-power efficient PSO based full adder in different technologies

Abstract

With the increasing complexity of electronic circuits and to meet the demand of high performance, the design and optimization of electronic circuits need to be automated with high degree of reliability and accuracy. In order to optimize hardware requirements of digital combinational circuits, evolutionary and innovative techniques need to be enforced at various levels such as at gate level and device level. One of the evolutionary technique Particle Swarm Optimization (PSO) algorithm motivated by the social behaviour of organism is used for the optimal design of combinational logic circuits with reduced gate count on MATLAB platform. PSO technique has been applied to optimize Full Adder circuit. Results are presented to support that the PSO based algorithm is better than Human Design Method in respect of time, labour and specially the gate count required to design digital combinational circuit. Later on that optimized circuit has been analysed by Microwind3.1 VLSI CAD Tool. Using the tool the parameters like Area, Power, Delay and Maximum and Average drain current are determined with 90nm, 65nm and 45nm technologies using BSIM4 Model. The results shown in this paper reflects that with technology scaling decreases the area, delay, power consumption and leakage current which are some of the major requirements of today's VLSI design.