Area-Delay-Energy aware SRAM memory cell and M × N parallel read/write memory array design for quantum dot cellular automata

Abstract

Quantum dot Cellular Automata (QCA) is an emerging nanotechnology, potentially suitable to replace the popular technologies like Complementary Metal Oxide Semiconductor (CMOS) technology. The evolution of QCA has become prominent due to high operating frequency, nanoscale device and zero current low power nanotechnology. However, the Area-Delay-Energy aware QCA logic circuit design remains a prime concern in this post CMOS technology. In this work the primary attention is given to build efficient QCA circuits. The motivation of this work is to propose Efficient VLSI design in terms of Area, Delay, Power and PDP (Power delay product). Different methodologies are reported to design a combinational and sequential circuit in QCA technology. An extensive focus is given in designing of 3 different QCA based Area-Delay-Energy aware SRAM memory cells, parallel read/write M × N SRAM memory array and peripherals like decoder and multiplexer. Since appropriate signal distribution network (SDN) is an essential aspect to deign QCA circuit, it has also been reported a delay aware signal distribution methodology applicable for any type of QCA logic circuit design. The significant results of this research finding are expressed in terms of Area-Delay-Energy dissipation tradeoff. When compared with respective to the state of art, the performance metric of proposed QCA based memory cells are excelled, on an average 40% reduction in area, 33% and 22% drop in delay and energy dissipation respectively are achieved for proposed three different memory cell design.