Area Overhead Analysis of SEF: A Design Methodology for Tolerating SEU

Abstract

Soft-Error filtering (SEF) is a design methodology proposed recently [1,2] for implementing machines tolerant to SEU. This paper deals mainly with the evaluation and the reduction of the area overhead brought by SEF. A new shift register filtering latch configuration is proposed. The use of this latch, optimized for minimum area, reduces the area overhead by a factor of 2.6, when compared with latches optimized for time performance. A detailed analysis of the area overhead with SEF implemented on two relatively complex machines produced the following results: a SEF version of the 6800 microprocessor would require an area overhead varying between 12% and 69% depending on the SEF latch used and, a SEF version of the RISCII microprocessor would result in a 38.8% area overhead. An analysis of the cost of implementing the Hamming error correcting code on a register array is presented and this cost is compared with that of implementing SEU tolerance directly with SEF. Finally, a hybrid approach is proposed where a large register array is protected by an error correcting code whereas the isolated latches are replaced by filtering latches. This hybrid approach reduces the area overhead to 18.8% for the RISCII architecture.