Area optimized architecture and VLSI implementation of RC5 encryption algorithm

Abstract

The rapid growth of the amount of transmitted data over wireless networks has triggered special needs for security. Today, wireless communications protocols have dedicated layers to ensure security in the transmission channel. Wireless transport layer security (WTLS) is widely used in both the wireless application protocol and open mobile alliance. Privacy in WTLS is based on the RC5 cipher. In this paper, an area optimized architecture and an FPGA implementation for RC5 is introduced. The proposed implementation allocates less area resources, with a range between 28 to 33%, compared with the conventional architecture. The proposed architecture has been designed with a pipeline technique, which achieves high speed performance. Finally, the proposed RC5 implementation is proved superior to other related works, compared in both frequency and throughput.