Abstract
Transistor regular layout (TRL) has been considered a more lithography-reliable approach for digital integrated circuit design than the most conventional standard cell design. However, the impact in circuit area seems to be unavoidable due to the loss in design flexibility. Hence, the decision in applying such design strategy depends not only on the expected yield improvement but also on the careful evaluation of circuit penalty. This paper presents an extensive analysis and discussion about area impact of TRL design style in comparison to the standard cell one. Several benchmark circuits were mapped by addressing specific cell libraries built for this purpose. Experimental results demonstrated that efficient TRL templates may minimize significantly the area overhead.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
