Abstract
We are developing a reconfigurable device MPLD whose basic structure is arrays of memory that function as Look-up Tables (LUTs) with n inputs and n outputs. In our MPLD architecture, these LUTs are directly interconnected with each other, so it doesn't require any reconfigurable switches for interconnections. And our developing MPLD has the possibility to map a logic circuit with smaller chip area compared with a conventional Field Programmable Logic Array (FPGA). In this paper, we compare the chip area required for mapping arithmetic units between our developing MPLD and a conventional FPGA.
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