Area efficient VLSI architecture for DCT using modified CORDIC algorithm

Abstract

Low-power layout is one of the most vital challenges to maximize battery life in portable devices and to save the energy during simulation operation. Image and video compressor is widely used in Discrete Cosine Transform (DCT). Many types of techniques are used in design discrete cosine transform (DCT). Multiplier and adder are two main components in design to DCT, Loeffer (1989) have developed a new architecture DCT, and it consists of 11 multiplications and 29 additions. By now a day we required low chip area and fast speed algorithm, but the multiplier consumed large area compared to adder. We are designed to multiplier less CORDIC (Coordinate Rotation Digital Computer) algorithm based on DCT. CORDIC is a main component of shift and add for rotation vector and plan which is usually used for calculation of trigonometric functions. CORDIC algorithm is efficient area and delay compared to existing algorithms. All designs are implementation Xilinx 14.1i and verified the result.