Area Efficient Multilayer Arithmetic Logic Unit Implementation in Quantum-dot Cellular Automata

Abstract

Quantum-dot Cellular Automata (QCA) is an innovative favorable calculation pattern nanoscale technology to design arithmetic digital circuits of any size and can be considered as a proper best alternative to digital Complementary Metal Oxide Semiconductor process. Also QCA provides a promising key for refining the computation results in numerous computational applications with high compaction density, and proficient in carrying out computations at ultra-high switching speeds. The key component present in Central Processing Unit is Arithmetic Logic Unit (ALU) which is used to execute several operations like arithmetic and logical operations, and the design of full adder circuits and low order multiplexer circuits of different sizes are important. In this proposed work, a QCA constructed full adder logic circuit based on five input majority gate is designed and simulated. A QCA constructed multilayer 1- bit ALU structure is designed in this paper which can implement both logical and arithmetic operations. To perform arithmetic operations a novel 2:1 multiplexer is proposed with reduced number of cell counts. Therefore, a 2:1 multiplexer is implemented in multilayer 1-bit ALU to reduce the overall cell count. Hence this proposed design of full-adder and other universal gates uses a reduced number of cells which in turn leads to reduced circuit size, and low power dissipation than the previous designs. The proposed architecture is simulated and verified using QCAD tool. The simulation results show that this proposed work shows superior performance in terms of circuit area and less number of cell counts.