Abstract
JPEG 2000 is an international standard for still images intended to overcome the shortcomings of the existing JPEG standard. Compared to JPEG image compression techniques, JPEG 2000 standard has not only better compression ratios, but it also offers some exciting features. As it's hard to meet the real-time requirement of image compression systems by software, it is necessary to implement compression system by hardware. In this paper we proposed an optimized architecture of bit plane coder for Embedded Block Coding with Optimal Truncation (EBCOT) algorithm. The proposed design is implemented on an FPGA platform. EBCOT is very important in the compression process of the JPEG 2000 standard. The proposed architecture is on four coding operations which are pipelined. The proposed architecture is implemented in a causal mode.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
