Area Efficient Floating Point Addition Unit With Error Detection Logic

Abstract

Applications that involve large dynamic range make use of the floating point operations. Addition is one of the complex operation in a floating point unit. This paper proposes an area efficient floating-point addition unit with error detection logic. Existing Leading Zero Anticipators (LZA) and error detection logics helps to reduce the delay of the general floating point unit, but are not area efficient. Here a single precision area efficient floating point addition unit is designed using an efficient Carry Select Adder together with the error detection logic. Efficient Carry Select Adder is developed using Binary to Excess-1 Converter instead of Ripple Carry Adder for cin=‘1’. The proposed design is simulated using ModelSim and is tested on Xilinx.