Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches

Abstract

This brief proposes an area-efficient bidirectional shift-register using bidirectional pulsed-latches. The proposed bidirectional shift-register reduces the area and power consumption by replacing master–slave flip-flops and 2-to-1 multiplexers with the proposed bidirectional pulsed-latches and non-overlap delayed pulsed clock signals, and by using sub shift-registers and extra temporary storage latches. A 256-bit bidirectional shift-register was fabricated using a 65 nm CMOS process. Its area was 1943 ${\boldsymbol {\mu }}\text{m}^{\boldsymbol {2}}$ and its power consumption is 200 ${\boldsymbol {\mu }}\text{W}$ at a 100 MHz clock frequency with $\text{V}_{\textbf {DD}}\boldsymbol {=}\boldsymbol {1.2}$ V. It reduces area by 39.2% and power consumption by 19.4% compared to the conventional bidirectional shift-register.