Abstract

A self-biased capacitor multiplier is proposed to reduce the area of a large integrating capacitor in loop filters. A prototype Σ−Δ fractional-N frequency synthesiser including the capacitor multiplier is fabricated with a 0.35 µm BiCMOS process. The designed capacitor multiplier makes capacitance of 2.72 nF from an on-chip capacitor of 170 pF with current consumption of 240 µA at 2.8 V. The frequency synthesiser demonstrates the in-band phase noise of −79 dBc/Hz at 5 kHz offset.

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