Area efficient and high-speed Galois field multiplier for mobile edge computing devices

Abstract

Mobile Edge Computing is one of the prominent technologies in 5G communication to improve throughput, scalability and reliability. In this work, area efficient and high-speed multipliers are implemented using finite field (Galois field) arithmetic which are widely utilised by edge computing devices. The performance of finite field multiplication operation is closely related to finite field elements representation. The proposed polynomial-based finite field bit parallel systolic array multiplier is able to achieve almost double the speed of existing multipliers. There is a considerable reduction in area and power for the proposed word-level normal basis finite field multiplier compared to the existing multipliers. The results clearly indicate that the proposed method improves the efficiency of finite field multipliers in terms of area, delay or power consumption. In order to process the real-time data efficiently, both the local computing and data offloading are carried out in developing a joint computation algorithm. The trade-off analysis between local computing and data offloading shows that local computing plays a more important role when the data size is small, but data offloading is preferred when the data size increases.