Area Efficient & High Performance Word Line Segmented Architecture in 7nm FinFET SRAM Compiler

Abstract

In 7nm TSMC FinFET nodes, metal resistance plays a critical role in achieving the best performance in SRAM design. Random variations and interconnect RC delay is increased due to the continual scaling of physical dimensions, which seriously degrades SRAM performance. In 7nm, it is being observed that Word line (WL) and Bit line resistance limits SRAMs to achieve the speed scaling that technology offers at SoC and Standard Cell library design level. Word line resistance plays a vital role in achieving better access time and operating frequency specifications. This paper proposes a High-Performance Word line segmented architecture that segments a wider memory array with minimum area impact. Based on the simulation results for a 7nm High Density, Single Port SRAM compiler, it was observed that the proposed architecture improved access time by 20% and operating frequency by 15%. Improved Word line RC also improves performance at high voltages when Read Assist (Word line underdrive) is enabled.