Area Efficient 64-Point Split Radix FFT using Single-Path Delay Feedback And Multi-Path Delay Commutator (SDF-MDC) Architecture

Abstract

Fast Fourier Transformation (FFT) is one of the basic operations in field of digital signal and image processing. Signal analysis, Data Compression, Sound Filtering, Partial differential equations, Multiplication of large integers, Image filtering are the important applications of the Fast Fourier Transform. In this paper, pipelined 64-point split radix Single-path Delay Feedback (SDF)-Multi-path Delay Commutator (MDC) FFT has been proposed. With the help of SDF and MDC data flow structures, the proposed FFT architectures are designed. A split radix FFT has lesser counts of adder and multiplication than the mixed radix FFT. These proposed architecture which is used to reduce the slices and LUTs and also increase the speed of the processor. The proposed architecture offers 16.82% reduction in slices, 34.05% reduction in slice registers, 54.67% reduction in flipflops, and 24.69% reduction in slice LUTs, 24.27% reduction in logic, 22.71% reduction in unused flipflops, 35.11% reduction LUT-flipflop pairs, and 60.25% reduction delay than the traditional 64-point mixed radix FFT. Simulation of proposed FFT architectures are done by using Model Sim 6.3C and performances are validated by using Xilinx Plan-ahead Integrated Circuit (IC) vendors.