Area and speed efficient floating point unit

Abstract

Earlier floating point number was not a common thing but with the advancement in Digital Signal Processors (DSPs), it is a common scene everywhere. Today's floating point arithmetic operations are very important in the design of DSPs and application-specific systems. As fixed-point arithmetic logics are faster and more area efficient, but sometimes it is desirable to implement calculation using floating-point numbers. In this paper, it presents a design of an area and speed efficient Floating Point Unit (FPU). FPU is a key element for real time computation of signals and real time data to meet real time scenario of signal processing, it is highly required to make computation faster as possible. It comes up with idea to design fast FPU. A Hybrid Field Programmable Gate Array (FPGA) has defined coarse- grained modules which use wide data paths. Selection FPGA affects the design in respect of area and speed so it chooses a hybrid FPGA for faster and area optimized computation. In this, it is using the modified Mitchell's algorithm for floating point multiplication and Euclidean algorithm for floating point division. In this, it has been observed that the floating point unit has been completely designed which performs various arithmetic operations like addition, subtraction, multiplication and division operations. It shows the improvement in area (in terms of slices) by 21.2%, 27.4% (in terms of LUTs) and 36.3% (in terms of IOBs) from the previous design.