Area and Power Improvement with New Initial Ordering Method Combined with Sift Algorithm for BDD Mapped Circuits

Abstract

Digital circuits are the important elements in almost every electronic design. As the size of electronic ICs are shrinking rapidly, the minimization of the circuit elements and power consumption became more focused area of VLSI research. In this paper, we have introduced a new method for reduction of area and power of binary decision diagram mapped circuits. Binary decision diagrams are used to represent digital functions in VLSI CAD. It is also used in physical modeling of digital circuits where each of the internal node of the diagram is represented using a single 2:1 MUX. In this work, a new initial ordering mechanism is proposed and combined with sift reordering method. The proposed method is implemented for different Boolean circuits from LGSynth93 benchmark suits. Buddy-2.4, which is a binary decision diagram manipulation tool, is used for BDD manipulations. The proposed method, which used an improved initial ordering with existing sift algorithm is implemented and compared with the results obtained from sift algorithm alone. The results obtained by this proposed method are found to be improvement over some of the best existing techniques. Keywords: Binary decision diagram, ordering technique, ADDER optimization