Area and memory efficient tunable VLSI implementation of DWT filters for image decomposition using distributed arithmetic

Abstract

ABSTRACT Dedicated hardware realisation of ‘Discrete Wavelet Transform’ (DWT) is highly demanded for real-time multimedia operations in any handheld gadgets, as DWT is a popular transform-domain mathematical tool widely employed for many applications. Several DWT techniques exist in the literature assisting the software-based DWT realizations, inappropriate for real-time operations. There exist several hardware-based solutions for DWT. But most of the VLSI architectures of DWT fail to offer balanced performance, i.e. such architectures show good performance with respect to certain metrics while sacrificing other performance metrics. In this article, a convolutional DWT-based pipelined and tunable VLSI architecture of Daubechies 9/7 and 5/3 DWT filter is presented. The proposed architecture is designed with an ardent focus of maintaining balanced performance. The presented design, which blends the merits of convolutional and lifting DWT while dumping their demerits, is prepared area and memory efficient by employing ‘Distributed Arithmetic’ (DA) in our own ingenious method. Comparative experimental results justify the superiority of the proposed design regarding 30% area reduction, memory saving, remarkable clock frequency attainment and acceptable computation time. The proposed 2D DWT architecture is applied for real-time image decomposition. The outcomes of such real-time on-board testing prove the practicability of the presented work.