ARE WE AT THE END OF CMOS SCALING?

Abstract

CMOS scaling enabled by advances in lithography has been behind the information revolution. Over the last 15 years, there has been a new CMOS technology node approximately every two years. The key feature of every node has been 2X density shrink and ~35% performance gain per technology node. At 90 nm node a number usual knobs that have enabled the scaling have approached their limits. Furthermore chip power (both active and stand-by) has been increasing rapidly, approaching air cool limit. Chip stand-by power, which was negligible a few years ago, is now about the same order of magnitude as the active power in high end microprocessors. In this talk it will be argued that because of power density limitation of 90 nm, 65 nm, and beyond nodes, performance and ability to shrink are more than ever linked, and in fact if the performance gain would significantly slow down (for the designs that operate at the existing cooling limit). It is more than ever critical to come up with technology features that will enhance the performance, at a given device leakage.