Architectures for hierarchical and other block matching algorithms

Abstract

Hierarchical block matching is an efficient motion estimation technique which provides an adaptation of the block size and the search area to the properties of the image. In this paper, we propose two novel special-purpose architectures to implement hierarchical block matching for real-time applications. The first architecture is memory-efficient, but requires a large external memory bandwidth and a large number of processors. The second architecture requires significantly fewer processors, but additional on-chip memory. We describe in details the processor architecture, the memory organization and the scheduling for both these architectures. We also show how the second architecture can be modified to handle full-search and 3-step hierarchical search block matching algorithms, with significant reduction in the hardware complexity as compared to existing architectures.