Architectures for digital filters using stochastic computing

Abstract

Stochastic computing has recently gained attention due to its fault-tolerance property. In stochastic computing, numbers are represented by probabilities of sequences. This paper addresses implementation of inner products and digital filters using stochastic logic. Straightforward implementations of stochastic inner products and digital filters lead to significantly large output error. To overcome this, this paper proposes a novel scaling method for efficient stochastic logic implementations of inner products and digital filters. By incorporating the filter coefficients into the probability of the selection signals of the multiplexors, the proposed weighted summation circuit can achieve better signal scaling with lower cost than the one derived from a traditional structure. This paper also presents how to vary the seeds in stochastic filters in order to reduce the correlation. Implementing IIR filters using stochastic logic limits possible pole locations. To overcome this, a new stochastic IIR filter structure is presented that includes a binary multiplier and stochastic-to-binary and binary-to-stochastic converters. Our experimental results show that the proposed architecture for the inner-product unit can lead to more than 12 times reduction in the error-to-power ratio. The stochastic FIR filters can perform the desired filtering function, but their accuracy degrades with the increase of filter order. The direct-form stochastic IIR filters may fail for large filter orders, but their performance can be improved by using cascade-form filter architecture.