Architectures and Synthesizers for Ultra-low Power Fast Frequency-Hopping WSN Radios

Abstract

1 Introduction. 1.1 Application field. 1.2 System requirements. 1.3 Energy scavenging techniques. 1.4 General wireless node requirements. 1.5 State of the art. 1.6 The objectives of this book. 1.7 Outline of the book. 2 System-Level and Architectural Trade-offs. 2.1 Modulation schemes for ultra-low power wireless nodes. 2.2 Optimal Data-rate. 2.3 Transmitter architectures. 2.4 Receiver architectures. 2.5 Conclusions. 3 FHSS Systems: State-of-the-art and Power Trade-offs. 3.1 Synchronization. 3.2 State-of-the-art Frequency Hopping Spread Spectrum (FHSS) systems. 3.3 Frequency Hopping (FH) synthesizer architectures. 3.4 Specifications for ultra-low-power frequency-hopping synthesizers. 3.5 PLL power estimation model. 3.6 Direct Digital Frequency Synthesizer (DDFS) power estimation model. 3.7 Summarizing discussion. 3.8 Conclusions. 4 A One-way Link Transceiver Design. 4.1 General guidelines for transmitter design. 4.2 Transmitter architecture. 4.3 Receiver architecture. 4.4 Implementation and experimental results. 4.5 Conclusions. 5 A Two-way Link Transceiver Design. 5.1 Transmitter design general guidelines. 5.2 Transmitter architecture. 5.3 Synthesizer design. 5.4 Generation of a 288-MHz reference clock. 5.5 Receiver design at system level. 5.6 Simulation and experimental results. 5.7 Conclusions. 6 Summary and conclusions. 7 Acronyms. Appendices. A Walsh based harmonic rejection sensitivity analysis. References.