Abstract
A ΣΔ ADC requires a set of two transfer functions to be implemented. In the widely-used case of the low-pass ADCs, the two functions are a high-pass noise transfer function (NTF) and a low-pass signal transfer function (STF). They are implemented with an architecture containing a loop filter and a coarse quantizer (with lower resolution than the Nyquist-rate target) which limits the applicability of the analytical (linear) model for the noise-shaping ADC [3]. These limits of linear model can only be overcome by time-domain simulations of the fully-designed architecture. Architecture-level issues of ΣΔ ADC design are covered in this Chapter, from effects of NTF and STF design choices to effects of circuit-related non-idealities like clock jitter, which are easy to model accurately at this abstraction level [4]. Section 2.1 describes the linear model, principles and operation of a ΣΔ ADC. In Section 2.2, the design of both singleloop and cascaded, discrete-time (DT) ΣΔ ADCs is covered. A similar analysis is carried out for the continuous-time (CT) ΣΔ ADCs in Section 2.3.
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