Abstract

This research presents architecture of Ultra Low Power (ULP) Micro Energy Harvester (MEH) using Radio Frequency (RF) signal as an input. RF has many advantages compared to other ambient sources because it is not affected by changes of weather or time, does not require heat or wind exposure and it can be moved randomly within the bound of the transmission source. When RF is used as the sole input, the designer needs to consider impedance matching as the most important element so that the antenna can transfer maximum power. The existing energy harvesters apply conjugate matching network as the current solution. However, this method causes some difficulties since the solution requires consideration of both voltage boosting and conjugate matching network simultaneously. To solve this problem, we propose ULP Radio Frequency Micro Energy Harvester (RFMEH) that will utilize a control loop as voltage boosting adjuster and network tuner to achieve maximum power transfer and minimum power reflection. The proposed architecture will also improve the RF-DC conversion efficiency and the sensitivity of the system. This is achieved using an efficient rectification scheme to convert RF to DC, DC-DC boost converter to increase the dc output voltage, adaptive control circuit to adjust the switching timing of boost converter, voltage limiter and regulator to produce the best output voltage. The proposed ULP RFMEH architecture will be designed and simulated using PSPICE software, Verilog coding using Mentor Graphics and functional verification using FPGA board (FPGA) before being implemented in CMOS 0.13 µm process technology. The proposed architecture will deliver approximately 2.45 V of output voltage from low input power level (-20 dBm) with an efficiency of more than 60%. This design will minimize the power consumption as compared to previous achievements and it can be applied in supplying power for health care monitoring systems or micro biomedical applications.

Highlights

  • In recent years, there is an increasing request for energy harvesting system that can provide input power to Ultra Low Power (ULP) sensor and wireless device

  • If the simulation results achieve the best result with no error especially in terms of efficiency, power consumption, input and output voltages, we will proceed to the behavioral model written in Verilog using Mentor Graphics

  • This optimized ULP Radio Frequency Micro Energy Harvester (RFMEH) design will be downloaded into the Field Programmable Gate Array (FPGA) board for functional verification

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Summary

Introduction

There is an increasing request for energy harvesting system that can provide input power to ULP sensor and wireless device. Ping-Hsuan and Tao (2013) achieved high Power Conversion Efficiency (PCE) on their design illustrated in Fig. 5 by implemented an efficient power path structure and low power implementation of the control circuit In this existing design, the rectifier’s PCE is optimized by adaptively adjusting the effective loading from the boost converter according to instant input power level. This study proposes a control loop to compensate any variation at the antenna-rectifier interface and maintain a resonance so that it can utilize maximum available input Another challenge is to maintain the optimal PCE value for the rectifier, by using an adaptive control circuit to control the switching timing of DC-DC boost which is inspired by Ping-Hsuan and Tao (2013). The regulator (block 8) will control or maintain the storage voltage to a constant value to power load circuit (Shokrani et al, 2014)

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