Architecture of 23GOPS video signal processor with programmable systolic array

Abstract

This paper describes an architecture of 23GOPS real-time video signal processor. In order to achieve high computational power and high data bandwidth for real-time video signal processing, we adopt a unique architecture based on a programmable systolic array with 90 video processing elements (VPEs). The VPE array realizes high processing ability and high flexibility by a simple structure of the VPE and a time-division multiple-operation scheme. It allows the processor to be applied to various real-time video signal processing like HD-TV (MUSE) decoding. The processor, called the digital filtering array, has been fabricated in 0.35-/spl mu/m CMOS three-metal-layer technology and achieves 23GOPS at 129.6 MHz operating frequency. Four million transistors are integrated in 13.61 mm/spl times/13.07 mm die size.