Architecture and design of a hardware accelerator for efficient 3D object recognition using the LC method

Abstract

Abstract The linear combination (LC) method is a powerful technique for 3D object recognition. The major computation involved in this method appears in the learning phase, where three sets of simultaneous linear equations must be solved for each observed image. Due to the high computational expense, the learning process is normally conducted off line, and sizes of the linear equation sets are usually kept small at the price of reduced accuracy. To make the LC method suitable for real-time 3D object recognition, the key issue is to expedite the learning process by reducing the time consumed in solving the simultaneous linear equations. To address this issue, we propose a hardware accelerator for solving sets of linear equations based on iterative methods. Using a single accelerator as a co-processor, a linear speedup can be obtained comparing with a single processor running the same type of equation solvers. By connecting multiple accelerators in parallel, computation time can be further reduced by at least an order of magnitude.