Abstract
Memory controller design is challenging as mixed time-criticality embedded systems feature an increasing diversity of real-time (RT) and non-real-time (NRT) applications with variable transaction sizes. To satisfy the requirements of the applications, tight bounds on the worst-case response time (WCRT) of memory transactions must be provided to RT applications, while the lowest possible average response time must be given to the remaining applications. Existing real-time memory controllers cannot efficiently achieve this goal as they either bound the WCRT by sacrificing the average response time, or cannot efficiently support variable transaction sizes. In this article, we propose to use dynamic command scheduling, which is capable of efficiently dealing with transactions with variable sizes. The three main contributions of this article are: (1) a memory controller architecture consisting of a front-end and a back-end, where the former uses a TDM arbiter with a new work-conserving policy and the latter has a dynamic command scheduling algorithm that is independent of the front-end, (2) a formalization of the timings of the memory transactions for the proposed algorithm and architecture, and (3) an analysis of WCRT for transactions to capture the behavior of both the front-end and the back-end. This WCRT analysis supports variable transaction sizes and different degrees of bank parallelism. The critical part of the WCRT is the worst-case execution time (WCET) of a transaction, which is the time spent on command scheduling in the back-end. The WCET is bounded by two techniques applied to both fixed and variable transaction sizes, respectively. We experimentally evaluate the proposed memory controller and compare to an existing semi-static approach. The results demonstrate that dynamic command scheduling significantly outperforms the semi-static approach in the average case, while it performs equally well or better in the worst-case with only a few exceptions. The former reduces the average response time for NRT applications, and the latter pertains the WCRT for RT applications.
Highlights
The complexity of mixed time-criticality system design is growing as an increasingly diverse mix of real-time and non-real-time (NRT) applications are integrated on the same platform
Since memory controllers typically consists of a front-end and a back-end (Akesson et al 2007; Krishnapillai et al 2014), the worst-case response time (WCRT) of a transaction is composed of the maximum interference delay caused by interfering transactions from other memory requestors in the front-end and its execution time consumed by scheduling commands in the back-end
A formalization of the dynamic command scheduling is proposed to capture the timings of commands, based on which the worst-case execution time (WCET) of transactions is defined
Summary
The complexity of mixed time-criticality system design is growing as an increasingly diverse mix of real-time and non-real-time (NRT) applications are integrated on the same platform. The diversity of applications and processing elements in such systems is reflected in the memory traffic going to the shared SDRAM, which features an irregular mix of transactions with variable sizes and heterogeneous requirements (Stevens 2010; Gomony et al 2014). A particular challenge when bounding the WCET of memory transactions is that the bound depends on the memory-map configuration, which is used to provide different trade-offs between bandwidth, execution time, and power consumption, by varying the number of banks that are used in parallel to serve a transaction (Goossens et al 2012). The architecture and basic operations of SDRAM memories are shown, and a general real-time memory controller that executes memory transaction by scheduling commands to the SDRAM is introduced
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