Architectural Synthesis of DSP Applications with Dynamically Reconfigurable Functional Units

Abstract

A great deal of research has been conducted in the area of scheduling DSP data flow graphs (DFG) onto multiprocessor systems. This paper introduces a new scheduling and allocation algorithm for the synthesis of DSP applications. The proposed technique provides the designer with a greater flexibility to explore the design space using a hybrid arithmetic functional unit library composed of both fixed operation-specific units and reconfigurable functional units capable of executing multiple operations. A novel reconfigurable multiplier called morphable multiplier is incorporated in the proposed synthesis technique. We show that moving from a fully homogenous multiprocessor design using fixed multiple-operation units (i.e., ALUs) to a fully heterogeneous design using fixed operation-specific units (i.e., adders or multipliers) results in decreasing the area of the design, but increasing the inter-processor communication overhead. However, a hybrid multiprocessor architecture that uses a hybrid arithmetic functional unit library composed of both fixed operation-specific units and run-time reconfigurable multiple-operation units brings about a trade-off between the area and the inter-processor communication overhead