Abstract
Studies on instruction-level parallelism (ILP) have shown that there are few independent instructions within the basic blocks of non-numerical applications. To uncover more independent instructions within these applications, instruction schedulers and microarchitectures must support the speculative execution of instructions. This paper describes an architectural mechanism for speculative execution called boosting. Boosting exploits ILP across conditional branches without adversely affecting the instruction count of the application or the cycle time of the processor. This paper also presents the results of a case study which found that boosting can take full advantage of the parallel execution resources within a superscalar microarchitecture. For this case study, we implemented a novel trace-based, global scheduling algorithm that supports various configurations of boosting hardware.
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