Architectural Implications of Reconfigurable Optical Interconnects

Abstract

We consider the influence of reconfigurable optical interconnects on computer architecture. A computer is viewed as a sea of interconnected logic gates, in which the interconnects are dynamically reconfigured during operation to suit the computation being performed. We explore reconfiguration at the gate level, at the processing element (PE) level, and at the system level. A significant finding is that the conventional von Neumann model of a digital computer may benefit from the use of reconfigurable interconnects at the gate level by implementing only the most recently used instructions in a function cache. By implementing only a subset of the instructions in a PE at any time, the physical size of the PE can be reduced and performance can be improved. The runtime behavior of programs executing on a uniprocessor is used as evidence that a function cache can be effective. Case studies are also provided for reconfiguration at the gate level and at the system level. The conclusion is made that reconfiguration can improve performance at all levels of the computer hierarchy, provided that the improvement in performance offsets the cost of reconfiguration.