Abstract
Architectural design and analysis of VIPER, a VLIW processor designed to take advantage of instruction level parallelism, are presented. VIPER is designed to take advantage of the parallelizing capabilities of Percolation Scheduling. The approach taken in the design of VIPER addresses design issues involving implementation constraints, organizational techniques, and code generation strategies. The hardware organization of VIPER is determined by analyzing the efficiency of various organizational strategies. The relationships that exist among the pipeline structure, the memory addressing mode, the bypassing hardware, and the processor cycle time are studied. VIPER has been designed to provide support for multiway branching and conditional execution of operations. An integral objective of the design was to develop the code generator for the target machine. The code generator utilizes a new code scheduling technique that is devised to reduce the frequency of pipeline stalls caused by data hazards.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
