Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors

Abstract

This work investigates the interrelation of performance and robustness against variability in industrial microprocessor designs. A novel analysis technique for variation-sensitive hardware and two figures of merit to quantify the robustness of a design against variations are proposed. Together with a multi-stage STA this enables an efficient application of low-V T cell insertion and pulsed latch design to compensate for within-die delay variations. For the same speed margin of 5% on design level, a pulsed latch design of an ARM926 microprocessor shows a 2.5× higher robustness compared to a MS-FF design with selective low-V T cell insertion.