Abstract
High speed multimedia applications have paved way for a whole new area in high speed error-tolerant circuits with approximate computing. These applications deliver high performance at the cost of reduction in accuracy. Furthermore, such implementations reduce the complexity of the system architecture, delay and power consumption. This paper explores and proposes the design and analysis of two approximate compressors with reduced area, delay and power with comparable accuracy when compared with the existing architectures. The proposed designs are implemented using 45 nm CMOS technology and efficiency of the proposed designs have been extensively verified and projected on scales of area, delay, power, Power Delay Product (PDP), Error Rate (ER), Error Distance (ED), and Accurate Output Count (AOC). The proposed approximate 4 : 2 compressor shows 56.80% reduction in area, 57.20% reduction in power, and 73.30% reduction in delay compared to an accurate 4 : 2 compressor. The proposed compressors are utilised to implement 8 × 8 and 16 × 16 Dadda multipliers. These multipliers have comparable accuracy when compared with state-of-the-art approximate multipliers. The analysis is further extended to project the application of the proposed design in error resilient applications like image smoothing and multiplication.
Highlights
The overhead on computation units in a processor to deliver high performance and execution efficiency can be leveraged by introducing approximation
SIMULATION RESULTS This section presents the analyses of the proposed 4 : 2 compressor architectures and 8 × 8, 16 × 16 Dadda multiplier designed with the proposed compressors
The analysis is carried out to determine the efficiency of the proposed designs, which is projected in terms of accuracy metrics and implementation efficiency metrics
Summary
The overhead on computation units in a processor to deliver high performance and execution efficiency can be leveraged by introducing approximation. Have proposed logic level approximation based architectures for 4 : 2 approximate compressor that are optimised for delay and power consumption. The authors have proposed a top-down structure for an approximate multiplier which dynamically allocates between the 8 : 2, 6 : 2 and 4 : 2 approximate compressors based on the partial product count. Reddy et al [25] have proposed a novel design for 4 : 2 compressor with an error rate of 12.5% This is achieved by relaxing the constraints on area, delay and power. A novel high speed area-efficient, low power 4 : 2 compressor architecture is proposed. A modified dual-stage compressor design is proposed to reduce area, delay and power dissipation in multipliers in which more than two stages of cascaded compressors are required for partial product accumulation.
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