Approximate Adder Tree Synthesis for FPGAs

Abstract

Compressor trees can be used as parts of larger arithmetic circuits in application-specific accelerators. Machine learning and other application domains that are amenable to approximate arithmetic can leverage approximate accelerators constructed from approximate arithmetic components. To this end, this paper introduces an approximate 8:3 parallel counter as a building block for approximate arithmetic. This specific parallel counter was chosen due to its compatibility of the logic block architectures present in modern commercial FPGAs, in particular, fracturable lookup tables (LUTs) and dedicated carry chains. To best exploit these features, a synthesis heuristic is proposed for approximate compressor tree synthesis, which introduces a move-and-duplicate transformation to increase parallel counter utilization. While prior (exact) compressor tree synthesis heuristics relied on a library of parallel counters, the approximate compressor tree synthesis heuristic introduced here employs the approximate 8:3 parallel counter in isolation. The experimental results reported demonstrate that approximate compressor trees use fewer logic resources and logic levels, in comparison to exact compressor tree synthesized using the same basic approach. This allows for a greater number of faster arithmetic operators to fit into a fixed-size device to maximize arithmetic throughput for a given level of accuracy.