Approaches to Area Efficient High-Performance Voltage-Controlled Oscillators in Nanoscale CMOS

Abstract

By optimizing the design of the inductor of a voltage-controlled oscillator for performance without the area constraint and fully filling the area underneath the inductor with other necessary components, the voltage-controlled oscillator performance, including area efficiency, can be simultaneously optimized. In addition to varactors and cross-coupled transistor pairs, a current source, VCO buffers, frequency dividers, and MOS bypass capacitors can be placed underneath an inductor of a VCO. Exploiting this, a 4.3-5.6-GHz VCO with an area of 14 400 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">A</sub> and FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TA</sub> of -202 and -210 dBc/Hz, respectively, have been demonstrated in a 65-nm CMOS process. The VCO performance is further improved by using nMOS-pMOS cross-coupled pairs and operating at 16-19 GHz, which are near the frequency at which the LC tank Q is near the maximum for the process. The output is frequency divided by four to generate signals at 4-4.8 GHz. These reduce the circuit area by ~3X. The circuit including all the components including a frequency divide-by-four circuit achieves FOMA and FOMTA of -209 and -214 dBc/Hz, respectively.