Applying transparent lossless data compression to improve the feasibility of using advanced error correction codes in solid-state drives

Abstract

As advanced error correction codes (ECC) which support soft decoding is suggested to use in the future NAND flash memories, the requirement of sensing and transferring multi-bit soft information from the flash cells to controller will incur a large read access latency. This paper proposes to exploit the lossless compressibility of files in LDPC coded NAND flash memories to reduce such latency overhead, other than saving storage space as in conventional practice. The key idea is to apply run-time lossless data compression to enable an opportunistic use of a stronger LDPC code with more coding redundancy, and trade such opportunistic extra error correction capability to allow more coarser-grained memory sensing and hence lead to less read response speed overhead without sacrificing the overall performance. Since the basic operation of NAND flash is typically realized in the unit of page (e.g., 4KB user data per page in the current NAND flash), we only apply this strategy to each individual page independently in order to be completely transparent to the firmware, operating systems and users. This paper quantitatively studies the effectiveness of this design strategy in 2bits/cell NAND flash memories. Results in the case study show that with this design strategy, up to 95.24% on-chip memory sensing latency reduction and 66.67% flash-to-controller data transfer latency can be achieved respectively.