Applying the adder inverting property in the design of cost-efficient reconfigurable logic

Abstract

Cost-efficiency (area, performance, power) is the key issue in the design of embedded systems. To satisfy this constraint, the intrinsic cost penalty of embedded reconfigurable logic (eRL) must be reduced. This paper proposes a novel multi-output LUT with four inputs and two outputs (4/2-LUT) which uses the adder inverting property to reach this goal. A logic block of the eRL architecture in which this technique is applied allows the cost-efficient implementation of random logic, datapath functions and small distributed memories.