Abstract
A multiple microprocessor (MMP) system can be defined as a system composed of two or more micro processors linked together by a certain system control to share a common memory, while each microprocessor is still capable of individual working with its own private memory. The main properties of a MMP system are simultaneously processing, efficient common memory bus utilization and distributed intelligences. The system control can be realized by time-sharing techniques, hardware logic devices, a central micro processor commander or the combination of the above to control the microprocessor switching, common memory bus accessing and common memory interface buffering. Since most microprocessors are not provided with the capabilities like: 1. bus hold/release output signal generating, 2. bus access granted/denied input control, 3. wait/off state before completing an instruction execution, most of the system controls are burdened with software design such as micro processor switching logic, flag test/set/reset se quence, vectored interrupt servicing, etc. Frequently the microprocessors are forced to enter into halt/ testing loop to wait for common memory accessing before a bus access granted signal is received. Complexity of the software program and inefficiency of its testing loop usually degrades the cost effectiveness of a MMP system. The SC/MP microprocessor (by National Semi conductor), having most of the multi-processor capability, can simplify software complexity when it is implemented in a MMP system. In this paper, several multiple SC/MP microprocessor systems will be proposed. Evaluation of these proposed systems with respect to hardware/software design will be discussed. Application of a MMP system in (a) single program, multiple data (b) multiple programs, single data will be illustrated.
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