Abstract

With the widespread diffusion of ubiquitous mobile computing and internet of things (IoT), secured communication and chip authentication become key requirements. Hardware-based security concepts generally provide the best performance in terms of good security standard, low power consumption, and large area density. In these concepts, the stochastic properties of the device, such as the physical and geometrical variations of the process, are harnessed to generate random bits and functions. This is the basis for the true-random number generator (TRNG), where true-random numbers are generated by exploiting the physics and randomness of nanoscale devices. The same random variations can also be used to implement physical unclonable function (PUF) for the authentication of individual hardware chips. Emerging memory devices rely on unique physical mechanisms for transport and switching, thus appear as the ideal source of entropy for hardware TRNG and PUF. These novel memory concepts include resistive switching memory (RRAM), phase change memory (PCM), and spin-transfer torque magnetic memory (STT-MRAM) devices. As these devices are increasingly adopted as memory and computing elements in several applications, exploiting their intrinsic stochastic variations for TRNG and PUF becomes an attractive solution for low-cost, high-performance security primitives. This chapter provides an overview of TRNG and PUF adopting emerging memory devices as the fundamental entropy source. TRNG concepts are classified by the microscopic stochastic variation that is adopted as entropy source, namely, current noise, switching delay time, or switching voltage. While most TRNG concepts rely on RRAM devices, we also show novel concepts using STT-MRAM devices which take advantage of the excellent endurance and speed of switching. The TRNG schemes are discussed in terms of the simplicity of the design, e.g., the ability to generate random bits without a probability tracking by adopting a differential circuit scheme. Finally, the status of PUF implementations using RRAM and their array circuits are presented and discussed.

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