Application of VRS Methodology for the Statistical Assessment of BTI in MG/HK CMOS Devices

Abstract

Variability induced by bias temperature instability is an increasing concern in aggressively scaled CMOS technologies. To assess the stochastic nature of the instability, we demonstrate that the recently introduced voltage ramp stress methodology properly captures the variance component and thus can be used to study stochastic effects related to transistor design and gate-stack processes.