Abstract
This paper presents a new gridless routing algorithm for solving obstacle detoured routing problem in physical design of VLSI circuits. Firstly, this algorithm maps a given routing instance to the corresponding graph model (path graph), which is a kind of asymmetric grid graph suitable for BBL (building block layout) mode layout. After that, we complete the main routing process based on an EACS (evolutionary ant colony system) algorithm in which the crossover operation in genetic algorithm (GA) is introduced into the ACS (ant colony system). Comparative simulation experiments with respect to the ACS demonstrate that the evolutionary parallel computation algorithm EACS is more effective than the original ACS algorithm in obstacle detoured routing of VLSI circuit physic al design.
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