Application and simulation of low temperature plasma processes in semiconductor manufacturing

Abstract

Integrated plasma equipment and feature scale models quantitatively describe broad classes of plasma process behavior. Metallization process models are the classic examples. This paper describes how multidimensional fundamentals-based models can be developed on diagnostics-friendly experimental tools and extended to commercial tools for applications with good confidence. First, the structure of integrated models used for the work described in this paper is discussed. This is followed by a description of the methodology employed in integrated model development. In addition to a metallization example, it is shown how complex dielectric etch models may be developed on the GEC reference cell and extended to commercial etchers with different yet similar physics. Plasma-surface interaction mechanisms may be required to be fine-tuned on actual tools with actual process material in order to capture the finesse in profile evolution when using a parameter space typical of a given manufacturing platform. Other examples described will be metallization pre-cleans, photoresist etch and a non-CMOS manufacturing example, deep Si etch for electron beam lithography mask making applications. Challenges to developing and applying integrated models are also discussed focusing on limitations in the ability to handle magnetized plasmas, electronegative plasmas, realistic external circuits and stiff numerics associated with describing plasmas over the disparate time and length scales that need to be handled.