Abstract
High-volume manufacturing of integrated circuits is what drives the semiconductor industry and the scaling of CMOS; however, shrinking all feature sizes is not optimal for all product volumes and applications. While scaling transistors provide improvement in performance at power in general, concerted scaling of the back-end-of-line (BEOL) interconnects provides improvement in density but at some expense of performance and quality. In this paper, we explore the benefits of relaxing the BEOL metal pitches as a tunable knob for application-specific optimization as a function of product volume. This paper demonstrates that a relaxed BEOL (r-BEOL) methodology can be applied at block level as well as chip level to provide performance and quality benefits while considering density constraints. The benefits of an r-BEOL pitch for power, timing, design for manufacturability, routing congestion, and signal integrity are considered for a 16-nm FinFET technology. Silicon results using relaxed M4–M7 metal layers are used to validate the simulation comparisons.
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